The present invention relates generally to memory circuits, and more particularly, to a memory architecture for supporting concurrent access of different types.
A typical embedded dynamic random access memory (DRAM) has a data width of 128 bits, which is divided into four 32-bit words. Consider the case, where there are four blocks (e.g., BLOCK0, BLOCK1, BLOCK2, BLOCK3) that access this memory. The blocks use the same row space but different column spaces for memory access. FIG. 1 illustrates a prior art memory configuration.
This memory architecture allows for concurrent access to all four columns when the access type is the same (i.e., when the operation for all four columns is all a read operation or when all the operation for all four columns is all a write operation). This restriction is referred to as an access-type restriction (i.e., only common access types can be performed concurrently).
Unfortunately, the access-type restriction incurs a significant time penalty. For example, when three of the four columns are of access type one and the fourth column is of access type two, two separate accesses or transfers are required. In other words, columns with different access types cannot be accessed concurrently, but instead must be performed in sequential order. As can be appreciated, the access-type restriction undesirably increases the time for memory accesses.
An example of a memory configuration that has this access-type restriction is the CMOS synchronous SRAM model TC59SM816 available from Toshiba, Inc.
Consequently, it would be desirable for a memory architecture that allows for supporting concurrent memory access of different types.
Based on the foregoing, there remains a need for a memory architecture for supporting concurrent access of different types.
According to one embodiment of the present invention, a memory architecture for supporting mixed-mode memory accesses. A common row address is provided. A first column address for accessing a first column and a second column address for accessing a second column are provided. A first write control signal for specifying one of a write access and a read access for the first column, and a second write control signal for specifying one of a write access and a read access for the second column are also provided. The memory architecture, responsive to these input signals, supports concurrent mixed-mode memory accesses to the first column and a write access to the second column.